1. Field of the Invention
An aspect of this disclosure relates to an anomaly detection method and a semiconductor manufacturing apparatus.
2. Description of the Related Art
In manufacturing a semiconductor, a wafer is processed while continuously monitoring signals indicating process conditions such as a pressure and a gas flow rate for each process recipe (which is hereafter simply referred to as a “recipe”). For each process condition, a normal range (which is defined by an upper limit and a lower limit) is predetermined. When a monitored signal is greater than the upper limit or less than the lower limit of the predetermined normal range, it is determined that an anomaly has occurred.
For example, Japanese Laid-Open Patent Publication No. 2008-515198 discloses a monitoring method used for anomaly detection during a semiconductor manufacturing process. Japanese Laid-Open Patent Publication No. 2008-515198 discloses that when a measured self-bias voltage is out of a predetermined bias voltage range, the measured self-bias voltage is correlated with, for example, an improper etching rate.
However, with the technologies disclosed in Japanese Laid-Open Patent Publication No. 2008-515198, small anomalies during wafer processing may not be detected depending on the setting of a specific value range indicating a normal range of the self-bias voltage. For example, when a wide normal range is set or a dead time, which is a predetermined time period where no anomaly detection is performed, is set between steps in a recipe, small anomalies during wafer processing may not be detected.